Introduction: MOS transistors, CMOS logic, basic gates and memory elements, CMOS fabrication and layout. MOS transistor theory: ideal (long-channel) I-V characteristics, C-V characteristics, non-ideal I-V effects, DC transfer characteristics. Delay: RC delay model, linear delay model – Logical Effort (for a single stage and for paths), transistor sizing. Power dissipation: dynamic power, static power, energy-delay optimization, low-power circuit design. Interconnect: wire geometry, metal layers, wire modeling, delay, energy, noise, wire engineering. Process and environmental variations. Scaling. Combinational circuit design: circuit families, circuit pitfalls. Sequential circuit design: circuit design of latches and flip-flops, max-delay constraints, min-delay constraints, time borrowing, clock skew. Semiconductor memories.

Students who successfully complete the course will be able to:

• Design static CMOS combinational and sequential logic at the transistor level and layout.
• Describe the general steps required for the fabrication of CMOS integrated circuits.
• Understand the accurate (non-ideal) MOS transistor behavior.
• Estimate and optimize combinational circuit delay using RC delay models and Logical Effort.
• Estimate and optimize interconnect delay and noise.
• Define the different kinds of power dissipation in VLSI circuits and use techniques to reduce it.
• Utilize different circuit families, aiming at either higher performance or smaller implementation area.
• Understand, describe and avoid common CMOS circuit pitfalls.
• Understand and describe the advantages and disadvantages of various sequencing elements, i.e., flip-flops, transparent latches, and pulsed latches.
• Understand and calculate max-delay constraints, min-delay constraints and the time that can be borrowed in all sequencing cases mentioned above.
• Describe the sources and effects of clock skew.
• Design and evaluate integrated circuits using Computer Aided Design (CAD) tools.
• Describe the structure and functionality of semiconductor memories.

Not required.

1. CMOS VLSI Design: A Circuits and Systems Perspective, Neil H. E. Weste and David M. Harris, 4th Edition
2. Digital Integrated Circuits: A Design Perspective, Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, 2nd Edition

• IEEE Transactions on VLSI Systems
• IEEE Transactions on Circuits and Systems I
• IEEE Transactions on Circuits and Systems II 

Lectures, Review-problem sessions, Laboratory hours, Homework, Project

Homework (30%), Project (30%), Written examination (40%)

Detailed information regarding the conduct and assessment of the course is available on the e-class platform (https://eclass.icsd.aegean.gr/courses/ICSD209/) and in the first lecture presentation.

Face-to-face