Application Specific Integrated Circuits (ASICs) and programmable devices (PLAs, PLDs, FPGAs), Hardware Description Languages (HDLs): Verilog and VHDL. Introduction to Verilog HDL, designing digital circuits with Verilog, Verilog syntax, modules and ports, structural modeling, behavioral modeling, dataflow modeling, tasks and functions. Finite State Machines (Mealy and Moore), Verilog for synthesis, design of sequential modules. Timing and delays in Verilog, Computer Aided Design (CAD) tools, logical simulation and timing verification. Random Access Memories (RAMs) and memory interfaces. Design prototyping.

Students who successfully complete the course will have:

• knowledge of the differences between programmable devices and Application Specific Integrated Circuits (ASICs),
• knowledge of the main features of Field Programmable Gate Arrays' (FPGAs') structure,
• the ability to use Verilog Hardware Description Language (HDL) for designing combinational and sequential digital circuits,
• the ability to write testbenches in Verilog,
• the ability to write Verilog for synthesis,
• the ability to simulate their designs,
• knowledge of the structure of RAMs and how to use them in digital systems,
• the skill to use prototyping boards for transferring their designs in hardware.

Not required.

1. Digital Design, A Systems Approach, W. J. Dally, R. C. Harting
2. FPGA-Based System Design, Wayne Wolf
3. Verilog HDL: A Guide to Digital Design and Synthesis, Samir Palnitkar, 2nd Edition

• IEEE Transactions on VLSI Systems
• IEEE Transactions on Computers
   

Lectures, Laboratory exercises, Project

Lab exercises (15%), Project (35%), Written examination (50%)

Detailed information regarding the conduct and assessment of the course is available on the e-class platform (https://eclass.icsd.aegean.gr/courses/ICSD403/) and in the first lecture presentation.

Face-to-face