Abstract
Energy systems monitoring is a key factor in reducing global energy consumption. Although intrusive approaches can be adopted, Non-Intrusive Load Monitoring (NILM), which targets estimation of individual-appliance consumption from aggregated electricity measurements, is the main choice for retrofitting the plethora of non-smart electrical installations. Contemporary NILM requirements include high-frequency power-line sampling, efficient disaggregation algorithms that can, potentially, run locally, on the monitoring device, to offload the remote fog/cloud infrastructure, and various open datasets to allow the development of such algorithms. Towards all these directions, in this paper, a versatile monitoring device to support NILM research is presented. It offers high sampling frequency, sufficiency of local resources, and has been designed to be used in different environments (residential, commercial, industrial). Actually, it was deployed in all these environments, with multiple copies of it being used in two different industrial facilities for over two years. The developed device’s cost has been kept low, its accuracy has been experimentally verified to be sufficiently high, while its key hardware characteristics, in the context of NILM research, compare favorably with those of other devices in the literature. Along with the device, a residential, high-frequency dataset is also presented and made publicly available.

Abstract
Non-Intrusive Load Monitoring (NILM) aims to determine individual-appliance energy consumption with minimum cost, by decomposing aggregated electricity measurements. Although important for achieving energy conservation and cost minimization, NILM requires high-frequency sampling rates to provide accurate results. This requirement significantly increases the need for storage and computational resources in the electric utility’s fog/ cloud infrastructure, and for bandwidth on the customer’s side. To resolve these issues, on-site disaggregation, i.e., on the monitoring device, can be employed. However, to keep device-cost low, lightweight NILM algorithms are needed. To this end, a lightweight event-detection algorithm designed to ease on-site implementation, on either software or hardware, is proposed. Event detection is the first, critical half of the well-established event-based NILM approach; it identifies appliance state changes (events). Although a few lightweight event-detection techniques, utilizing high-frequency data, have been presented in the literature, their performance is relatively low in complex-load cases. The proposed algorithm utilizes simple-to-compute features and employs multiple simple criteria to declare an event as detected, and slope-coefficient inspection to identify steady states. Moreover, it can detect events with very small time difference between them. Comparisons show that its performance is superior even against more complex event-detection approaches, while its low computational cost is also verified.

Abstract
While logic locking is a promising defense to protect hardware designs, many attacks have been shown to undermine its security by retrieving the secret key. All the powerful attacks rely on a working chip, i.e., an oracle, and in particular, heavily use the test access. The proposed technique DisORC turns the oracle into a dishonest one whenever a potential attack is detected. DisORC works on the premise that structural testing of chips need not be performed with the correct functionality. We implement this capability by adding circuitry around a logic-locked design that reconfigures its functionality upon detecting access to scan chains. Any attempt to access scan chains disconnects the secret key from the circuit, and clears all of its traces, isolating and securing it. We also pair this defense with a truly random logic locking (TRLL) scheme that makes random decisions in inserting key gates and retaining signal polarities without relying on any logic synthesis technique to perform bubble pushing. Any netlist analysis-based attack, known or anticipated, will then learn nothing useful to infer the key values. The combined defense DisORC + TRLL thwarts oracle-based and netlist analysis-based attacks while delivering sufficient corruption levels at the outputs. We also show that the proposed defense is cost effective and can be integrated into the design flow easily. The proposed logic locking defense provides protection against untrusted foundry, testing facility, end users, and any combination of them colluding together.

Abstract
The prevalence of wireless networks has made the long-term need for communications security more imperative. In various wireless applications, images and/or video constitute critical data for transmission. For their copyright protection and authentication, watermarking can be used. In many cases, the cost of wireless nodes must be kept low, which means that their processing and/or power capabilities are very limited. In such cases, low-cost hardware implementations of digital image/video watermarking techniques are necessary. However, to end up with such implementations, proper selection of watermarking techniques is not enough. For this reason, in this paper, we introduce computation optimizations of the implemented algorithm to keep the integer part of arithmetic operations at optimal size, and, hence, arithmetic units as small as possible. In addition, further analysis is performed to reduce quantization error. Three different hardware-architecture variants, two for image watermarking and one for video (pipelined), are proposed, which reutilize the already small arithmetic units in different computation steps, to further reduce implementation cost. The proposed designs compare favorably to already existing implementations in terms of area, power, and performance. Moreover, the watermarked images'/frames' errors, compared to their floating point counterparts, are very small, while robustness to various attacks is high.

Abstract
Large systems-on-chip (SoCs) and chip multiprocessors (CMPs), incorporating tens to hundreds of cores, create a significant integration challenge. Interconnecting a huge amount of architectural modules in an efficient manner, calls for scalable solutions that would offer both high throughput and low-latency communication. The switches are the basic building blocks of such interconnection networks and their design critically affects the performance of the whole system. So far, innovation in switch design relied mostly to architecture-level solutions that took for granted the characteristics of the main building blocks of the switch, such as the buffers, the routing logic, the arbiters, the crossbar’s multiplexers, and without any further modifications, tried to reorganize them in a more efficient way. Although such pure high-level design has produced highly efficient switches, the question of how much better the switch would be if better building blocks were available remains to be investigated. In this paper, we try to partially answer this question by explicitly targeting the design from scratch of new soft macros that can handle concurrently arbitration and multiplexing and can be parameterized with the number of inputs, the data width, and the priority selection policy. With the proposed macros, switch allocation, which employs either standard round robin or more sophisticated arbitration policies with significant network-throughput benefits, and switch traversal, can be performed simultaneously in the same cycle, while still offering energy-delay efficient implementations.

Abstract
Defect screening is a major challenge for nanoscale CMOS circuits, especially since many defects cannot be accurately modeled using known fault models. The effectiveness of test methods for such circuits can therefore be measured in terms of the coverage obtained for unmodeled faults. In this paper, we present a new defect-oriented dynamic LFSR reseeding technique for test-data compression. The proposed technique is based on a new output-deviation metric for grading stuck-at patterns derived from LFSR seeds. We show that, compared to standard compression-driven dynamic LFSR reseeding and a previously proposed deviation-based method, higher defect coverage is obtained using stuck-at test cubes without any loss of compression.

Abstract
Even though test set embedding (TSE) methods offer very high compression efficiency, their excessively long test application times prohibit their use for testing systems-on-chip (SoC). To alleviate this problem we present two new types of linear feedback shift registers (LFSRs), the Single-State-Skip and the Variable-State-Skip LFSRs. Both are normal LFSRs with the addition of the State-Skip circuit, which is used instead of the characteristic-polynomial feedback structure for performing successive jumps of constant and variable length in their state sequence. By using Single-State-Skip LFSRs for testing single or multiple identical cores and Variable-State-Skip LFSRs for testing multiple non-identical cores we get the well-known high compression efficiency of TSE with substantially reduced test sequences, thus bridging the gap between test data compression and TSE methods.

Abstract
Various compression methods have been proposed for tackling the problem of increasing test-data volume of contemporary, core-based systems. Despite their effectiveness, most of the approaches that are based on classical codes (e.g., run-lengths, Huffman) cannot exploit the test-application-time advantage of multiple-scan-chain cores, since they are not able to perform parallel decompression of the encoded data. In this paper, we take advantage of the inherent parallelism of Huffman decoding and we present a generalized multilevel Huffman-based compression approach that is suitable for cores with multiple scan chains. The size of the encoded data blocks is independent of the slice size (i.e., the number of scan chains), and thus it can be adjusted so as to maximize the compression ratio. At the same time, the parallel data-block decoding ensures the exploitation of most of the scan chains’ parallelism. The proposed decompression architecture can be easily modified to suit any Huffman-based compression scheme.

Abstract
A new statistical test data compression method that is suitable for IP cores of an unknown structure with multiple scan chains is proposed in this paper. Huffman, which is a well-known fixed-to-variable code, is used in this paper as a variable-to-variable code. The precomputed test set of a core is partitioned into variable-length blocks, which are, then, compressed by an efficient Huffman-based encoding procedure with a limited number of codewords. To increase the compression ratio, the same codeword can be reused for encoding compatible blocks of different sizes. Further compression improvements can be achieved by using two very simple test set transformations. A simple and low-overhead decompression architecture is also proposed.

Abstract
Selective Huffman coding has recently been proposed for efficient test- data compression with low hardware overhead. In this paper, we show that the already proposed encoding scheme is not optimal and we present a new one, proving that it is optimal. Moreover, we compare the two encodings theoretically and we derive a set of conditions which show that, in practical cases, the proposed encoding always offers better compression. In terms of hardware overhead, the new scheme is at least as low-demanding as the old one. The increased compression efficiency, the resulting test-time savings, and the low hardware overhead of the proposed method are also verified experimentally.

Abstract
A new test-data compression method suitable for cores of unknown structure is introduced in this paper. The proposed method encodes the test data provided by the core vendor using a new, very effective compression scheme based on multilevel Huffman coding. Each Huffman codeword corresponds to three different kinds of information, and thus, significant compression improvements compared to the already known techniques are achieved. A simple architecture is proposed for decoding the compressed data on chip. Its hardware overhead is very low and comparable to that of the most efficient methods in the literature. Moreover, the major part of the decompressor can be shared among different cores, which reduces the hardware overhead of the proposed architecture considerably. Additionally, the proposed technique offers increased probability of detection of unmodeled faults since the majority of the unknown values of the test sets are replaced by pseudorandom data generated by a linear feedback shift register.

Abstract
In this paper, a new reseeding architecture for scan-based built-in self-test (BIST), which uses a linear feedback shift register (LFSR) as test pattern generator, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan chain of the circuit under test in different test phases. The LFSR generates the same state sequence in all phases, keeping that way the implementation cost low. A seed-selection algorithm is furthermore presented that, taking advantage of the multiphase architecture, manages to significantly reduce the number of the required seeds for achieving complete (100%) fault coverage. The proposed technique can be used either in a full BIST implementation or in a test-resource partitioning scenario, since the test-data storage requirements on the tester are very low. When a full BIST implementation is preferable, the multiphase architecture can also be combined with a dynamic reseeding scheme that uses combinational logic instead of a ROM in order to perform the reseedings. This way the implementation area of the BIST circuitry is further reduced. Experimental results demonstrate the advantages of the proposed LFSR reseeding approach over the already known reseeding techniques.

Abstract
Low power dissipation (PD) during testing is emerging as one of the major objectives of a built-in self-test (BIST) designer. In this paper we examine the testability of multipliers based on Booth encoding and Wallace tree summation of the partial products and we present a methodology for deriving a low power BIST scheme for them. We propose several design rules for designing the Wallace tree in order to be fully testable under the cell fault model. The proposed low power BIST scheme for the derived multipliers is achieved by: (a) introducing suitable test pattern generators (TPGs), (b) properly assigning the TPG outputs to the multiplier inputs and (c) significantly reducing the test set length. Results indicate that the total power dissipated, the average power per test vector and the peak PD during testing can be reduced up to 73%, 27% and 36% respectively with respect to earlier schemes, depending on the implementation of the basic cells and the size of the multiplier. The test application time is also significantly reduced, while the introduced BIST scheme implementation area is small.

Abstract
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the reseeding is performed on-the-fly by inverting the logic value of some of the bits of the next state of the Test Pattern Generator (TPG). The proposed reseeding technique is generic and can be applied to TPGs based on both Linear Feedback Shift Registers (LFSRs) and accumulators. An efficient algorithm for selecting reseeding points is also presented, which targets complete fault coverage and allows to well exploiting the trade-off between hardware overhead and test length. Using experimental results we show that the proposed method compares favorably to the other already known techniques with respect to test length and the hardware implementation cost.

Abstract
Logic locking has received a lot of attention in the literature due to its very attractive hardware-security characteristics: it can protect against IP piracy and overproduction throughout the whole IC supply chain. However, a large class of logic-locking attacks, the oracle-based ones, take advantage of a functional copy of the chip, the oracle, to extract the key that protects the chip. So far, the techniques dealing with oracle-based attacks focus on the netlist that the attacker possesses, assuming that the oracle is always available. For this reason, they are usually overcome by new attacks. In this paper, we propose a hardware security scheme that targets the protection of the oracle circuit, by locking the circuit when the, necessary for setting the inputs and observing the outputs, scan in/out process begins. Hence, no correct input/output pairs can be acquired to perform the attacks. The proposed scheme is not based on controlling global signals like test_enable or scan_enable, whose values can be easily suppressed by the attacker. Security threats are identified, discussed and addressed. The developed scheme is combined with a traditional logic locking technique with high output corruptibility, to achieve increased levels of protection.

Abstract
This paper presents the progress of PREDIVIS project, on the development of a novel energy disaggregation hardware/software tool towards energy efficiency and predictive maintenance. The PREDIVIS project involves the use of an edge-cloud hybrid computing architecture, hardware accelerated algorithms, machine/deep learning, and big data approaches for the analysis of high frequency electrical loads. The project will deliver an advanced and innovative solution for energy disaggregation intended for industrial applications, commercial buildings and households. A main scope of the project is to address the problem of predictive maintenance by providing a cost-efficient solution with industry 4.0 features.

Abstract
In many resource/ power constrained applications (e.g., in wireless-network nodes) there is a need for low cost hardware implementations of digital image watermarking techniques. However, to end up with such an implementation, a proper selection of a watermarking technique, based on performance and cost criteria, is not enough. For that reason, in this paper we introduce computation optimizations of the implemented algorithm to keep the integer portion of arithmetic operations at optimal size, and, hence, arithmetic units as small as possible. Additionally, the proposed architecture reutilizes those units in different computation steps, to further reduce implementation cost. The proposed design compares favorably with the already existing implementations, in terms of area, power and performance.

Abstract
Logic locking has been successfully used for protecting digital circuits against IC piracy. Modern logic locking techniques offer significant security advantages, like high corruptibility of the locked circuit's outputs when applying random keys (= 50% Hamming Distance -HD- compared to the correct outputs), or resilience to the key-sensitization attack. However, there are no techniques to combine both advantages. To solve this problem, weighted logic locking is proposed in this paper. Instead of the conventional single key-input control, the proposed technique uses multiple key-inputs to control every key-gate. This new, weighted key-gate control is by construction immune to the key-sensitization attack, while by employing a new key-gate insertion metric, 50% HD is obtained even for circuits with many outputs. Additionally, weighted key-gate control increases dramatically the probability of any key-gate to corrupt the circuit’s values, which means that fewer key-gates are needed to achieve 50% HD. This way, execution time for locking the circuits is drastically reduced. Apart from these advantages, weighted logic locking is fairly "generic" and can be combined with other techniques to improve security (e.g., to thwart the SAT attack).

Abstract
Since Arduino is the main entry-level platform to the world of electronic circuits and systems, there are many programming environments that try to ease the burden of Arduino textual programming on young primary students. Although block-based, most of these environments retain the imperative structures of textual programming languages, which are not easily comprehensible by such students. The proposed, in this paper, Learning-Arduino-With-Rules Introductory System (LAWRIS) tries to tackle this problem by adopting a rule-based approach: an Arduino-based pre-specified system can be programmed by constructing rules with very simple and intuitive jigsaw pieces, in a visual, web-based environment. Contrary to other programming environments for Arduino, the main logic of LAWRIS is implemented on the board side and only a configuration string is downloaded to it. Thus, LAWRIS features fast responses to both circuit input changes and program modifications, a very important characteristic for young students. It also imposes minimal overhead on the host system, allows web access of the programming environment, and has very low hardware cost.

Abstract
Network-on-Chip (NoC) design tries to keep a balance between network performance and physical implementation flexibility. The adoption of Virtual Channels (VC) holds promise for scalable NoC design. VCs allow for traffic separation and isolation, enable deadlock avoidance and improve network performance. In this paper, we present ElastiNoC, a novel distributed VC-based router architecture that enjoys all the benefits offered by VCs and leads to efficient silicon-aware implementations. The proposed architecture utilizes an efficient buffering strategy and allows for modular pipelined organizations that increase the clock frequency. Moreover, it offers maximum freedom in terms of physical placement, by allowing the NoC components to be physically spread throughout the chip, irrespective of the network topology. The combined effect of all supported features enables significant delay reductions under equal performance, when compared to state-of-the-art VC-based NoC implementations. Moreover, the careful addition of self-test structures allows ElastiNoC to enjoy fully distributed Built-In Self Testability (BIST), where testing unfolds in phases and reaches high fault coverage with small test application time.

Abstract
On-chip interconnection networks simplify the increasingly challenging process of integrating multiple functional modules in modern Systems-on-Chip (SoCs). The routers are the heart and backbone of such networks, and their implementation cost (area/power) determines the cost of the whole network. In this paper, we explore the time-multiplexing of a router’s output ports via a folded datapath and control, where only a portion of the router’s arbiters and crossbar multiplexers are implemented, as a means to reduce the cost of the router without sacrificing performance. In parallel, we propose the incorporation of the switch-folded routers into a new form of heterogeneous network topologies, comprising both folded (time-multiplexed) and unfolded (conventional) routers, which leads to effectively the same network performance, but at lower area/energy, as compared to topologies composed entirely of full- fledged wormhole or virtual-channel-based router designs.

Abstract
On-chip interconnection networks simplify the integration of complex system-on-chips. The switches are the basic building blocks of such networks and their design critically affects the performance of the whole system. The transfer of data between the inputs and the outputs of the switch is performed by the crossbar, whose active connections are decided by the arbiter. In this paper, we design scalable dynamic-priority arbiters that are merged with the crossbar’s multiplexers. The proposed RTL macros can adjust to various priority selection policies, while still following the same unified architecture. With this approach, sophisticated arbitration policies that yield significant network-throughput benefits can be implemented with negligible delay cost relative to the standard round-robin policy.

Abstract
Reliable operation that can be checked on-line is of paramount importance to current and future systems-on-chips that are implemented in very deep submicron technologies. In such systems, the communication among architectural modules is handled by a modular network-on-chip infrastructure that should be sufficiently protected from transient faults that may affect its correct operation. The error protection mechanism should cover all fault scenarios and incur the minimum area/energy/delay overhead. In this paper, we propose such an on-line checking mechanism for the switch allocator of the router that detects every possible single transient or permanent fault in the arbiters and handles it appropriately, thus preserving the reliable operation of the switch.

Abstract
Soft on-FPGA interconnection networks are gaining increasing importance since they simplify the integration of heterogeneous components and offer, at the same time, a modular solution to the complex system-wide communication issues. The switches are the basic building blocks of such interconnection networks and their design critically affects the performance of the whole network. The way data traverse each switch is governed by the operation of the arbiter and the crossbar’s multiplexers that need to be efficiently mapped on the FPGA fabric under tight area and delay constraints. This paper explores the design space of an arbiter and a multiplexer as a unified entity and proposes two new circuit alternatives that allow the design of scalable soft FPGA switches.

Abstract
Although LFSR reseeding based on test cubes for modeled faults is an efficient test compression approach, it suffers from the drawback of limited, and often unpredictable, coverage of unmodeled defects. We present a new defect coverage-driven window-based LFSR reseeding technique, which offers both high test quality and high compression. The efficiency of the proposed encoding technique in detecting defects is boosted by an efficient "output deviations" metric for grading the calculated LFSR seeds. We show that, compared to standard compression-driven LFSR reseeding, higher defect coverage is obtained without any loss of compression.

Abstract
The main disadvantage of LFSR-based compression is that it should be usually combined with a constrained ATPG process, and, as a result, it cannot be effectively applied to IP cores of unknown structure. In this paper, a new LFSR-based compression approach that overcomes this problem is proposed. The proposed method allows each LFSR seed to encode as many slices as possible. For achieving this, a special purpose slice, called stop-slice, that indicates the end of a seed's usage is encoded as the last slice of each seed. Thus, the seeds include by construction the information of where they should stop and, for that reason, we call them self-stoppable. A stop-slice generation procedure is proposed that exploits the inherent test set characteristics and generates stop slices which impose minimum compression overhead. Moreover, the architecture for implementing the proposed technique requires negligible additional hardware overhead compared to the standard LFSR-based architecture. The proposed technique is also accompanied by a seed calculation algorithm that tries to minimize the number of calculated seeds.

Abstract
It is well-known that the high compression efficiency of test set embedding is compromised by its long test application times. To alleviate this problem we present a sophisticated version of the recently proposed State Skip LFSRs, the Variable-State Skip (VSS) LFSRs. By using VSS LFSRs successive jumps of variable lengths can be performed in the state sequence of the LFSRs and thus the useless parts of the test sequences can be effectively skipped. A low-overhead decompression architecture, that overcomes the limitations of simple State Skip LFSRs, is also proposed. The combination of VSS LFSRs with the proposed architecture offers the very small test-data volumes of test set embedding, with drastically shortened test sequences. Also, in a multi-core environment where a common decompressor is used, maximum test-sequence-length reduction can be achieved for every individual IP core that is tested.

Abstract
We present a new type of Linear Feedback Shift Registers, State Skip LFSRs. State Skip LFSRs are normal LFSRs with the addition of a small linear circuit, the State Skip circuit, which can be used, instead of the characteristic-polynomial feedback structure, for advancing the state of the LFSR. In such a case, the LFSR performs successive jumps of constant length in its state sequence, since the State Skip circuit omits a predetermined number of states by calculating directly the state after them. By using State Skip LFSRs we get the well-known high compression efficiency of test set embedding with substantially reduced test sequences, since the useless parts of the test sequences are dramatically shortened by traversing them in State Skip mode. The length of the shortened test sequences approaches that of test data compression methods. A systematic method for minimizing the test sequences of reseeding-based test set embedding methods, and a low overhead decompression architecture are also presented.

Abstract
A new efficient statistical test data compression method, suitable for IP cores of unknown structure with multiple scan chains is proposed. Huffman, which is a well known fixed-to-variable code, is used in this paper as a variable-to-variable code. The pre-computed test set of a core is partitioned into variable-length blocks, which are then compressed by an efficient Huffman-based encoding procedure with a limited number of codewords. For increasing the compression ratio, the same codeword can be reused for encoding compatible blocks of different sizes. Further compression improvements can be achieved by using two very simple test-set transformations. A low-overhead decompression architecture is also proposed.

Abstract
Various efficient compression methods have been proposed for tackling the problem of increased test-data volume of contemporary, core-based Systems-on-Chip (SoCs). However, many of them cannot exploit the test-application-time advantage that cores with multiple scan chains offer, since they are not able to perform parallel decompression of the encoded data. For eliminating this problem, we present a new, low-overhead decompression scheme that can generate clusters of test bits in parallel. The test data are encoded using a recently proposed and very effective compression method called multilevel Huffman. Thus, apart from the significantly reduced test-application times, the proposed approach offers high compression ratios, as well as increased probability of detection of unmodeled faults, since the majority of the unspecified bits of the test sets are replaced by pseudorandom data. The time/space advantages of the proposed approach are validated by thorough experiments.

Abstract
In this paper we introduce a new test-data compression method for IP cores with unknown structure. The proposed method encodes the test data provided by the core vendor using a new, very effective compression scheme based on multilevel Huffman coding. Specifically, three different kinds of information are compressed using the same Huffman code, and thus significant test data reductions are achieved. A simple architecture is proposed for decoding on-chip the compressed data. Its hardware overhead is very low and comparable to that of the most efficient methods in the literature. Additionally, the proposed technique offers increased probability of detection of unmodeled faults since the majority of the unknown values of the test set are replaced by pseudorandom data generated by an LFSR.

Abstract
In this paper a new test set embedding method with reseeding for scan-based testing is proposed. The bit sequences of multiple cells of an LFSR, which is used as test pattern generator, are exploited for effectively encoding the test set of the core under test (multiphase architecture). A new algorithm which comprises four heuristic criteria is introduced for efficiently selecting the required seeds and LFSR cells. Also, a cost metric for assessing the quality of the algorithm's results is proposed. By using this metric, the process of determining proper values for the algorithm's input parameters is significantly simplified. The proposed method compares favorably with the most recent and effective test set embedding techniques in the literature.

Abstract
In this paper a new approach that targets the reduction of both the test-data volume and the scan power during the testing of a core is proposed. For achieving the two aforementioned goals, a novel algorithm that inserts some inverters in the scan chain(s) of the core under test (CUT) is presented. The proposed algorithm targets the maximization of run-lengths of zeros (or ones) in the test set accompanying the CUT, while imposing no performance or area penalty since the negated outputs of the scan flip-flops can be used for performing the necessary inversions. This algorithm combined with the Minimum Transition Count mapping of don't cares in a test set, as well as with the alternating run-length code that have been recently proposed, achieves better test-data compression and reduced scan-power results than the relative works in the literature.

Abstract
In this paper we present an efficient seed-selection algorithm for reducing the test-data storage requirements of scan-based, test set embedding schemes with reseeding. Moreover, a technique for reducing the length of the generated test sequences is introduced. This technique achieves significant savings with minor overhead (one extra bit per seed plus a small counter in the scheme’s control logic). Experimental results demonstrate the advantages of the proposed algorithm and the test sequence reduction technique.

Abstract
A novel technique for reducing the test sequences of reseeding-based schemes is presented in this paper. The proposed technique is generic and can be applied to test set embedding or mixed-mode schemes based on various TPGs. The imposed hardware overhead is very small since it is confined to just one extra bit per seed plus one very small counter in the scheme'’s control logic, while the test-sequence-length reductions achieved are up to 44.71%. Along with the test-sequence-reduction technique, an efficient seed-selection algorithm for the test-per-clock, LFSR-based, test set embedding case is presented. The proposed algorithm targets the minimization of the selected seed volumes and, combined with the test-sequence-reduction technique, delivers results with fewer seeds and much smaller test sequences than the already proposed approaches.

Abstract
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan chain in different test phases. The LFSR generates the same state sequence in all phases, keeping that way the implementation cost low. Also, a dynamic reseeding scheme is adopted for further reducing the required hardware overhead. A seed-selection algorithm is moreover presented that, taking advantage of the multi-phase architecture, manages to reduce the number of the required seeds for achieving complete (100 %) fault coverage. Experimental results demonstrate the superiority of the proposed LFSR reseeding approach over the already known reseeding techniques.

Abstract
In this paper we present a new LFSR reseeding scheme for scan-based BIST suitable for circuits with random-pattern-resistant faults. The proposed scheme eliminates the need of a ROM for storing the seeds since the reseedings are performed dynamically by inverting some selected bits of the LFSR register. A time-to-market efficient algorithm is also presented for selecting the reseeding points in the test sequence, as well as a proper seed at each point. This algorithm targets complete fault coverage and minimization of the resulting test length and hardware overhead. Experimental results on ISCAS '85 and ISCAS '89 benchmark circuits demonstrate the advantages of this new LFSR reseeding approach in terms of area overhead and test application time.

Abstract
In this paper we propose a new algorithm for seeds selection in LFSR-based test-per-clock BIST. The proposed algorithm uses the well-known concept of solving systems of linear equations and, based on heuristics, minimizes the number of seeds and test vectors while achieving 100% fault coverage. Experimental results indicate that it compares favorably to the other known techniques.

Abstract
In this paper we present a new reseeding technique for LFSR-based test pattern generation suitable for circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the LFSR jumps from a state to the required state (seed) by inverting the logic value of some of the bits of its next state. An efficient algorithm for selecting reseeding points is also presented, which targets complete fault coverage and minimization of the cardinality of the test set and the hardware required for the implementation of the test pattern generator. The application of the proposed technique to ISCAS '85 and the combinational part of ISCAS '89 benchmark circuits shows its superiority against the already known reseeding techniques with respect to the length of the test sequence and, in the majority of cases, the hardware required for their implementation.

Abstract
The low power as a feature of a BIST scheme is a significant target due to quality as well as cost related issues. In this paper we examine the testability of multipliers based on Booth encoding and Wallace tree summation of the partial products and we present a methodology for deriving a low power Built In Self Test (BIST) scheme for them. We propose several design rules for designing the Wallace tree in order to be fully testable under the cell fault model. The proposed low power BIST scheme for the derived multipliers is achieved by: (a) introducing suitable Test Pattern Generators (TPG), (b) properly assigning the TPG outputs to the multiplier inputs and (c) significantly reducing the test set length with respect to earlier schemes. Our results indicate that the total power dissipated during test can be reduced from 64.8% to 72.8%, while the average power per test vector can be reduced from 19.6% to 27.4% and the peak power dissipation can be reduced from 16.8% to 36.0%, depending on the implementation of the basic cells and the size of the multiplier. The test application time is also significantly reduced, while the introduced BIST scheme implementation area is small.

Abstract
The number of physical paths in a carry save or modified Booth multiplier, as well as in a non restoring cellular array divider is prohibitively large for testing all paths for delay faults. Besides, neither all paths are robustly testable nor a basis consisting of SPP-HFRT paths exists. In this paper we present sufficient modifications of the above mentioned circuits so that a basis consisting of SPP-HFRT paths to exist, The cardinality of the derived basis is very small. Also, hardware and delay overheads due to the modifications are respectively small and negligible.

Abstract
Testing of Modified Booth Multipliers (MBMs) with respect to path delay faults, is studied in this paper. Design modifications are proposed and a path selection method is suggested. The selected paths are Single Path Propagating – Hazard Free Robustly Testable (SPP-HFRT) and based on their delays the delay along any other path of the MBM can be calculated. The number of the selected paths is impressively small compared to all paths of the multiplier. The delay and hardware overhead imposed by the modifications are respectively negligible and small.

Abstract
This paper studies path delay fault testing of Omega Multistage Interconnection Networks (MINs). Taking advantage of the MIN’s parallelism, we show that although the number of physical paths is O(n^2), all these paths can be tested optimally for path delay faults applying O(n) test vector pairs. Having derived the test set, we also show how the test set application as well as the response verification can be done either by a dedicated low–cost tester or on-line using the system resources.